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Please use this identifier to cite or link to this item: http://hdl.handle.net/11133/879

Title: 組合せ論理回路のハード的一致検査方式の提案
Other Titles: クミアワセ ロンリ カイロ ノ ハードテキ イッチ ケンサ ホウシキ ノ テイアン
Coincidence Detecting Scheme for the Combinatorial Logic Circuits
Authors: 羽賀, 隆洋
立木, 滋也
HAGA, Takahiro
TSUIKI, Shigeya
Issue Date: 31-Mar-1991
Publisher: 愛知工業大学
Abstract: In this paper, we propose an error detecting hardware-scheme for the combinatorial logic circuits (the scheme is named by us as the Coincidence Detecting Scheme). Compared with the software-type testing, the hardware-type detecting has sveral merits such as (1) simultaneous detection of the errors when they occur, doing usual operations, (2) the possibility of detecting the intermittent faults, etc. But, it is very important to make the detecting circuit to be small one, for the reliability and the frugality of the detecting circuit. Hence, AND-Inverse, Output-Side AND Detecting Schemes are proposed as the special cases of the Coincidence Detecting Scheme. And, as a result, it is shown that (1) AND-Inverse Detecting Scheme has minimal redundancy (2 AND and 1 EXOR elements are sufficient excepting NOT), (2) Output-Side AND Detecting Scheme can be applicable to any given combinatorial logic circuit which is detected, and (3) the (average) detecting rate is largely improved by using parallel extensions of such schemes. Of course, above results hold under the situation that any stuck-at faults (at input and/or output points) can be detected.
URI: http://hdl.handle.net/11133/879
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