SDRAMをメインメモリとするMIPS-CPUのFPGA化

Abstract

In the year of 2003, our laboratory designed CPU of MIPS architecture, one of the representative RISC architectures, in order to study design methodology of a CPU, and implemented it in FPGA. The CPU adopted SRAMs in the FPGA as a main memory. As a next step, a MIPS-CPU with a SDRAM as a main memory has been studied. SDRAM controller module has been designed to cope with the specific features of SDRAMs such as refreshing, address multiplexing, access latency and so on. Designed CPU module has been impemented in a FPGA. The highest operation frequency is found to be 82.50MHz with a program of small steps.