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Please use this identifier to cite or link to this item: http://hdl.handle.net/11133/1242

Title: SDRAMをメインメモリとするMIPS-CPUのFPGA化
Other Titles: FPGA implementation of MIPS CPU with SDRAM as a main memory
Authors: 森川, 良
堀田, 厚生
HOTTA, Atsuo
Issue Date: 31-Mar-2005
Publisher: 愛知工業大学
Abstract: In the year of 2003, our laboratory designed CPU of MIPS architecture, one of the representative RISC architectures, in order to study design methodology of a CPU, and implemented it in FPGA. The CPU adopted SRAMs in the FPGA as a main memory. As a next step, a MIPS-CPU with a SDRAM as a main memory has been studied. SDRAM controller module has been designed to cope with the specific features of SDRAMs such as refreshing, address multiplexing, access latency and so on. Designed CPU module has been impemented in a FPGA. The highest operation frequency is found to be 82.50MHz with a program of small steps.
URI: http://hdl.handle.net/11133/1242
Appears in Collections:40号

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