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Please use this identifier to cite or link to this item: http://hdl.handle.net/11133/1216

Other Titles: Implementation of MIPS CPU in FPGA
Authors: 杉野, 晃洋
堀田, 厚生
SUGINO, Akihiro
HOTTA, Atsuo
Issue Date: 31-Mar-2004
Publisher: 愛知工業大学
Abstract: The multi-cycle system and the pipelined architecture designed 32-bit CPU which used the MIPS architecture in order to study the design technique of CPU. It is made to implement in the product 'EP1S10F780C7ES' of the stratix series which is one of the highly efficient FPGA devices of ALTERA. The design of a multi-cycle system and a pipelined architecture was performed, and both performance comparison was performed. MIPS CPU of a multi-cycle system operated by 61.60MHz. MIPS CPU of a pipelined architecture operated by 42.90MHz. A general performance ratio is considered that an about 2.60-time performance ratio is obtained.
URI: http://hdl.handle.net/11133/1216
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