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Please use this identifier to cite or link to this item: http://hdl.handle.net/11133/1037

Title: (p,q)論理を応用した10値全加算器の一構成法
Other Titles: P Q ロンリ オ オウヨウシタ 10チ ゼンカサンキ ノ イチコウセイホウ
Realization of 10 Valued Full Adder utilizing the (p,q)-Logic
Authors: 長谷川, 忠光
羽賀, 隆洋
HASEGAWA, Tadamitsu
HAGA, Takahiro
Issue Date: 31-Mar-1998
Publisher: 愛知工業大学
Abstract: In this paper, it is proposed that the p-valued full adder is realized by the (p, q)-adic・min・max scheme which is rather low cost. It is also shown, However, that the circuit cost varies largely with the numbering of the vertices of full adder whitch is p-valued logical function.
URI: http://hdl.handle.net/11133/1037
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